Case Study Ieee 802 11abgn

Wireless IoT LoRa Private Network Gateway

Preliminary
  • Qualcomm Atheros Quard-Core ARM Cortex-A7 SoC
  • Built-in Dual Band Concurrent Wi-Fi MU-MIMO (2x2)
  • LPWAN LoRa Private (WISE-Link) Connectivity
  • WAN x1 / LAN x1 Gigabit Ethernet
  • Integration of Modbus TCP and Modbus RTU networks
  • IPSec / L2TP VPN Traffic Encryption
  • Rich Network Scanrio by S/W Configuration
  • Modularization hardware design
  • OpenWRT BSP embeded
  • Web UI user interface

データシート(PDF)ダウンロードオンラインで購入システム構成

WISE-3610 is Qualcomm ARM Cortex A based hardware platform, which is operating at OpenWRT, described as a Linux distribution for embedded devices. The Advantech WISE-3610 Industrial Router is Advantech IoT gateway design for smart city, Industrial 4.0 applications, even those in harsh environment, leveraging wireless sensor technology. This IoT gateway can aggregate both the wireless sensor networks (WSN), including Low Power WAN (LPWAN) technology by Advantech private LoRa technology, wired sensors and ties them into an IP network. With modular slot design, it can agilely adapt to a variety of wireless technologies at regional RF bands, wireless communication protocol by various uplink requirement and quickly go to market.

製品詳細 (4) 詳細ダウンロード

Memory

  • Technology

    WISE-3610ILS-51A1CDDR3L 1600 MHz
    WISE-3610ILS-51A1EDDR3L 1600 MHz
    WISE-3610ILS-51A1JDDR3L 1600 MHz
    WISE-3610ILS-51A1NDDR3L 1600 MHz
  • Capacity

    WISE-3610ILS-51A1COn-board DDR3L 256MB
    WISE-3610ILS-51A1EOn-board DDR3L 256MB
    WISE-3610ILS-51A1JOn-board DDR3L 256MB
    WISE-3610ILS-51A1NOn-board DDR3L 256MB
  • Flash

    WISE-3610ILS-51A1C128 NAND Flash
    WISE-3610ILS-51A1E128 NAND Flash
    WISE-3610ILS-51A1J128 NAND Flash
    WISE-3610ILS-51A1N128 NAND Flash

Processor

  • CPU

    WISE-3610ILS-51A1CQCA Quad-core ARM Cortex A7 CPU 716 MHz
    WISE-3610ILS-51A1EQCA Quad-core ARM Cortex A7 CPU 716 MHz
    WISE-3610ILS-51A1JQCA Quad-core ARM Cortex A7 CPU 716 MHz
    WISE-3610ILS-51A1NQCA Quad-core ARM Cortex A7 CPU 716 MHz

Ethernet

  • Chipset

    WISE-3610ILS-51A1CQCA8075 PSGMII
    WISE-3610ILS-51A1EQCA8075 PSGMII
    WISE-3610ILS-51A1JQCA8075 PSGMII
    WISE-3610ILS-51A1NQCA8075 PSGMII
  • Speed

    WISE-3610ILS-51A1C2 x 10/100/1000Mbps
    WISE-3610ILS-51A1E2 x 10/100/1000Mbps
    WISE-3610ILS-51A1J2 x 10/100/1000Mbps
    WISE-3610ILS-51A1N2 x 10/100/1000Mbps
  • PoE

    WISE-3610ILS-51A1CN/A
    WISE-3610ILS-51A1EN/A
    WISE-3610ILS-51A1JN/A
    WISE-3610ILS-51A1NN/A

WSN

  • Standard

    WISE-3610ILS-51A1CLoRa Private Network - WISE-Link
    WISE-3610ILS-51A1ELoRa Private Network - WISE-Link
    WISE-3610ILS-51A1JLoRa Private Network - WISE-Link
    WISE-3610ILS-51A1NLoRa Private Network - WISE-Link
  • Network Topology

    WISE-3610ILS-51A1CStar
    WISE-3610ILS-51A1EStar
    WISE-3610ILS-51A1JStar
    WISE-3610ILS-51A1NStar
  • WSN Network size

    WISE-3610ILS-51A1C500 nodes

Memory

  • Technology
  • Capacity
  • Flash
  • DDR3L 1600 MHz
  • DDR3L 1600 MHz
  • DDR3L 1600 MHz
  • DDR3L 1600 MHz
  • On-board DDR3L 256MB
  • On-board DDR3L 256MB
  • On-board DDR3L 256MB
  • On-board DDR3L 256MB
  • 128 NAND Flash
  • 128 NAND Flash
  • 128 NAND Flash
  • 128 NAND Flash

Processor

Ethernet

WSN

  • Standard
  • Network Topology
  • WSN Network size
  • Frequency Band
  • Number of Channel
  • Channel Separation
  • Raw Data Rate
  • Output Power
  • LoRa Private Network - WISE-Link
  • LoRa Private Network - WISE-Link
  • LoRa Private Network - WISE-Link
  • LoRa Private Network - WISE-Link
  • 500 nodes
  • 500 nodes
  • 500 nodes
  • 500 nodes
  • 470~510 MHz
  • 863-870MHz
  • 920-928MHz
  • 902-928MHz
  • 200 KHz
  • 200 KHz
  • 200 KHz
  • 200 KHz / 600 KHz
  • 5470 bps
  • 50000 bps
  • 5470 bps
  • 5470 bps / 21900 bps
  • 17 dBm
  • 14 dBm
  • 13 dBm / 20 dBm
  • 20 dBm

Wireless

Graphics

RTC

Watchdog Timer

Indicator and Button

  • GPIO
  • Audio
  • USB
  • CANBus
  • I2C
  • Button
  • LED
  • Mini PCIe Socket
  • Serial Port
  • SD Socket
  • Switch
  • 1 x USB 3.0
  • 1 x USB 3.0
  • 1 x USB 3.0
  • 1 x USB 3.0
  • 1 reset button for system reboot
  • 1 reset button for system reboot
  • 1 reset button for system reboot
  • 1 reset button for system reboot
  • 6, PWR/LoRa/Wi-Fi 2G/Wi-Fi 5G/USB/WWAN
  • 6, PWR/LoRa/Wi-Fi 2G/Wi-Fi 5G/USB/WWAN
  • 6, PWR/LoRa/Wi-Fi 2G/Wi-Fi 5G/USB/WWAN
  • 6, PWR/LoRa/Wi-Fi 2G/Wi-Fi 5G/USB/WWAN
  • 1 Full size mini PCIe slot
  • 1 Full size mini PCIe slot
  • 1 Full size mini PCIe slot
  • 1 Full size mini PCIe slot
  • 1 x RS-232/422/485 (DB9 Male)
  • 1 x RS-232/422/485 (DB9 Male)
  • 1 x RS-232/422/485 (DB9 Male)
  • 1 x RS-232/422/485 (DB9 Male)
  • 1 x microSD socket
  • 1 x microSD socket
  • 1 x microSD socket
  • 1 x microSD socket

Expansion

Power

  • DC-input
  • Power Consumption (Max)
  • Power Type
  • DC 9~24V
  • DC 9~24V
  • DC 9~24V
  • DC 9~24V

Environment

  • Operational Temperature
  • Operating Humidity
  • -20 ~ 70° C
  • -20 ~ 70° C
  • -20 ~ 70° C
  • -20 ~ 70° C
  • 10% ~ 95% @ 40°C relative humidity, non-condensing
  • 10% ~ 95% @ 40°C relative humidity, non-condensing
  • 10% ~ 95% @ 40°C relative humidity, non-condensing
  • 10% ~ 95% @ 40°C relative humidity, non-condensing

Mechanical

  • Dimensions (with a metal plate)
  • Dimensions (without a metal plate)
  • Mounting
  • Weight
  • 213.5 x 150 x 44 mm
  • 213.5 x 150 x 44 mm
  • 213.5 x 150 x 44 mm
  • 213.5 x 150 x 44 mm
  • 188 x 150 x 39 mm
  • 188 x 150 x 39 mm
  • 188 x 150 x 39 mm
  • 188 x 150 x 39 mm
  • Metal bracket wall mount
  • Metal bracket wall mount
  • Metal bracket wall mount
  • Metal bracket wall mount

Operating System

Certification

  • QCA Quad-core ARM Cortex A7 CPU 716 MHz
  • QCA Quad-core ARM Cortex A7 CPU 716 MHz
  • QCA Quad-core ARM Cortex A7 CPU 716 MHz
  • QCA Quad-core ARM Cortex A7 CPU 716 MHz
  • QCA8075 PSGMII
  • QCA8075 PSGMII
  • QCA8075 PSGMII
  • QCA8075 PSGMII
  • 2 x 10/100/1000Mbps
  • 2 x 10/100/1000Mbps
  • 2 x 10/100/1000Mbps
  • 2 x 10/100/1000Mbps
  • 2x2 IEEE802.11a/b/g/n/ac MU-MIMO 2.4GHz / 5GHz
  • 2x2 IEEE802.11a/b/g/n/ac MU-MIMO 2.4GHz / 5GHz
  • 2x2 IEEE802.11a/b/g/n/ac MU-MIMO 2.4GHz / 5GHz
  • 2x2 IEEE802.11a/b/g/n/ac MU-MIMO 2.4GHz / 5GHz
  • Option for 3G/LTE card
  • Option for 3G/LTE card
  • Option for 3G/LTE card
  • Option for 3G/LTE card
  • 6 x SMA
  • 6 x SMA
  • 6 x SMA
  • 6 x SMA
  • 2 x Micro SIM slot
  • 2 x Micro SIM slot
  • 2 x Micro SIM slot
  • 2 x Micro SIM slot
  • OpenWRT Barrier Breaker (Linux 3.14)
  • OpenWRT Barrier Breaker (Linux 3.14)
  • OpenWRT Barrier Breaker (Linux 3.14)
  • OpenWRT Barrier Breaker (Linux 3.14)
  • SRRC/NCC/TELEC/CE/FCC/IC Class B
  • SRRC/NCC/TELEC/CE/FCC/IC Class B
  • SRRC/NCC/TELEC/CE/FCC/IC Class B
  • SRRC/NCC/TELEC/CE/FCC/IC Class B

IEEE 802.3 CSMA/CD Protocol

Contents

Related publications: [KNSW04, KNSW07]

Introduction

This case study concerns probabilistic model checking of certain aspects of the IEEE 802.3 CSMA/CD (Carrier Sense, Multiple Access with Collision Detection) protocol. The CSMA/CD protocol is designed for networks with a single channel and specifies the behaviour of stations with the aim of minimising simultaneous use of the channel (data collision).

The basic structure of the protocol is as follows: when a station has data to send, it listens to the medium, after which, if the medium was free (no one transmitting), the station starts to send its data. On the other hand, if the medium was sensed busy, the station waits a random amount of time and then repeats this process.

This case study is used to test the feasibility of the symbolic (zone based) model checking algorithms introduced in [KNSW04, KNSW07] for checking probabilistic timed automata against PTCTL (Probabilistic Timed Computation Tree Logic) specifications. For comparison we also include the results obtained with the integer semantics approach in PRISM [KNS03b, KNPS03].

Prototype Implementation of [KNSW04, KNSW07]

We now briefly summarise our prototype implementation of the model checking algorithms of [KNSW04, KNSW07]. It is important to note that the aim of our implementation is to validate the algorithms presented for model checking probabilistic timed automata against PTCTL, rather that to devise an efficient implementation; the latter will be the subject of future work.

The main step in the implementation of our techniques is the representation of (sets of) symbolic states and the operations required on them; more precisely, since a symbolic state is a pair (l,ζ) where l is a location of the probabilistic timed automaton and ζ is a zone (polyhedron), we require a method for representing zones and performing operations on zones.

Difference Bound Matrices (DBMs) [Dil89] are a well known data-structure for the representation of convex zones and are used in the model checkers UPPAAL and KRONOS. As the operations required by our algorithm can introduce non-convexity, we must represent non-convex zones. Following the approach presented in [Tri98], we represent non-convex zones by lists of DBMs, that is, we represent a non-convex zone ζ by a list of convex zones ζ1,...,ζn such that ζ= ζ1 ∪ ... ∪ ζn. It thus follows that a symbolic state can be represented by a location and a list of DBMs.

This representation is clearly not canonical: there are many ways of decomposing a non-convex zone into a set of convex zones. However, [Tri98] presents algorithms for the operations we require when zones are represented as lists of DBMs. Based on [Tri98], we have implemented, in Java, a prototype DBM package and the operations on lists of DBMs required by the model checking algorithms of [KNSW04, KNSW07].

Probabilistic Timed Automata Model

The model we consider here is a probabilistic extension of the timed automata model given in [NSY92]. We consider the case when there are two stations trying to send data at the same time, and the overall model is given by the parallel composition of three probabilistic timed automata representing the medium and two stations trying to send data.

The medium:

The probabilistic timed automaton representing the medium is given below.

The medium is initially ready to accept data from any station (event send). Once a station starts sending its data there is an interval of time (at most σ), representing the time it takes for a signal to propagate between the stations, in which the medium will accept data from the other station (resulting in a collision). After this interval, if the other station tries to send data it will get the busy signal (busy). When a collision occurs, there is a delay (again at most σ) before the stations realize there has been a collision, after which the medium will become free (represented by the event cd). If the stations do not collide, then when a station finishes sending it data (event end) the medium becomes idle.

The stations

The probabilistic timed automaton representing a single station is given below. Note that, as in [NSY92] we assume that only packets of equal length are sent and we denote by λ the time to send a data packet.

A station starts by sending is data (we are modelling the case when initially the stations collide). If there is no collision, then, after λ time units, the station finishes sending its data (event end). On the other hand, if there is a collision (event cd), the station attempts to retransmit the packet where the scheduling of the retransmission is determined by a truncated binary exponential backoff process. The delay before retransmitting is an integer number of time slots (each of length slotTime). The number of slots that the station waits after the nth transmission failure is chosen as a uniformly distributed random integer in the range:

0 , 1 , 2 , ... , 2k+1-1

where k=min(n,bcmax). Once this time has elapsed, if the medium appears free the station resends the data (event send), while if the medium is sensed busy (event busy) the station repeats this process.

Note that, to simplify the model, we have removed the limit on the number of times a station attempts to retransmit a packet as specified in the standard. For our experiments we consider the cases when bcmax is either 1 or 2.

Parameters:

The following parameters are taken from the IEEE standard 802.3 for 10 Mbps Ethernet.

  • Propagation delay σ=26μs.
  • Time to send a data packet (plus the propagation delay) λ=808μs.
  • Length of one time slot (used in the truncated binary exponential backoff process) slotTime=2σs.

Analysis results

We now report on the model checking results obtained using our prototype implementation for the following performance measures:

Since the algorithms work via backwards reachability and the model is constructed as the parallel composition of subcomponents, the prototype tool first performs a forwards reachability step to find the set of reachable locations (taking 19.77 seconds).

Due to the size of the deadline models, all experiments concerning the digital clocks approach were performed with PRISM's MTBDD engine.

Probabilistic reachability

The following probabilistic reachability property has been verified.

  • "With probability 1, eventually both stations send their packet correctly."

In PTCTL this is expressed by: P≥1[ trueU done ]

Model checking times:

The algorithm MaxV≥1 of [KNSW04, KNSW07]returns no symbolic states, which implies that the minimum probability is 1. Below we give the model checking statistics for MaxV≥1 as we vary the parameter c.

c:time (s):MaxV≥1 iters:MaxU≥1 iters:
1 1,048 9667,409
10 106.7 99 755
26 48.38 40 321
30 44.31 35 281
40 34.06 27 218
50 29.88 22 184
60 88.01 21 168
70 79.83 18 150
80 72.39 16 141
90 72.17 15 123
100 66.20 13 121
200 57.18 7 87
808 474.9 4 89

In contrast when using the digital clocks approach and PRISM, the model has 5,240 states, it takes 25.46 seconds to construct the model and 12.99 seconds to perform the verification.

c:
time (s):MaxV≥1 iters:MaxU≥1 iters:
1 2,0581,070 7,830
10 223.1 109 800
26 126.6 44 347
30 142.4 38 303
40 109.6 29 237
50 94.77 24 201
60 213.6 22 177
70 179.3 19 157
80 149.5 16 136
90 158.3 16 130
100 115.6 14 117
200 232.6 9 93
808 21,682 5 147

In contrast when using the digital clocks approach and PRISM, the model has 17,763 states, it takes 46.22 seconds to construct the model and 21.67 seconds to perform the verification.

Time-bounded probabilistic reachability

We consider the following time-bounded probabilistic reachability property:

  • "the minimum/maximum probability of both stations correctly delivering their packets by the deadline D".

In PTCTL this is expressed by: z.P[ trueU done & z≤D ]

Computing maximum probabilities

Maximum probabilities are computed through the algorithm MaxU (see [KNSW04, KNSW07]), where the final step requires the calculation of maximum reachability probabilities on a finite state system which we perform with PRISM.

D:MaxUPRISMmaximum probability:
time (s):iters:states:construction time (s):model checking
time (s):iters:
10001.1779 71 - - - 0.0
120011.7013191 - - - 0.0
140026.5117311 - - - 0.0
160055.6521431 - - - 0.0
180076.6832617 7.6330.075470.729165
200084.3338725 9.1120.123580.929361
220098.8248861 13.540.192710.988106
2400120.558997 17.980.259840.997999
2600145.3681,12926.500.362920.999663
2800174.2781,26335.590.446990.999941
3000239.8881,39942.360.534990.999988

Below are the model checking statistics for the digital clocks approach when verifying this property with PRISM.

D:constructionmodel checkingmaximum probability:
time (s):states:time (s):iters:
1000141.71,876,105 0.0740 0.0
1200243.32,671,305 0.0990 0.0
1400307.83,546,505 0.12 0 0.0
1600391.84,501,705 0.14 0 0.0
1800445.55,528,692 291.11,8460.729165
2000513.86,570,692 612.52,0130.929361
2200583.57,612,692 847.12,2340.988106
2400658.28,654,692 969.12,4550.997999
2600670.29,696,692 1,2292,6730.999663
2800700.210,738,6921,4862,8860.999941
3000764.311,780,6921,7033,0970.999988
D:MaxUPRISMmaximum probability:
time (s):iters:states:construction time (s):model checking
time (s):iters:
10002.1769 91 - - - 0.0
1200178.011423 - - - 0.0
1400833.413759 - - - 0.0
1600192.6151,095 - - - 0.0
1800337.8211,83490.310.065390.580428
2000600.6242,615232.90.161440.903011
2200655.9293,019323.40.262500.986651
2400706.7343,415437.10.349550.998157
2600773.9393,795541.70.459580.999743
28008,762444,183740.90.570610.999961
30009,852494,579901.70.700610.999990

Below are the model checking statistics for the digital clocks approach when verifying this property with PRISM.

D:constructionmodel checkingmaximum probability:
time (s):states:time (s):iters:
1000238.84,170,287 0.1180 0.0
1200331.55,813,169 0.1520 0.0
1400442.37,535,969 0.1850 0.0
1600532.89,338,769 0.2190 0.0
1800639.311,211,180483.51,8380.580428
2000727.913,072,580953.21,9980.903011
2200818.814,930,1801,4092,2130.986651
24001,03616,787,7803,0282,4250.998157
26001,37918,645,3803,3132,6350.999743
28001,97320,502,9802,9312,8430.999961
30001,26122,360,5804,3042,9990.999990
Computing minimum probabilities

Minimum probabilities are computed through the algorithms MaxV≥1 and MaxU, where the final step of the MaxU requires the calculation of maximum reachability probabilities which we again perform with PRISM.

For comparison we also consider an alternative approach for calculating minimum probabilities if deadline properties which reduces the problem to computing maximum probabilities on a modified model. More precisely, since eventually both stations send their packet correctly with probability 1, we can use the technique given in [KNS03b] and instead compute the minimum probability of satisfying the property

  z.P[ trueU done & z≤D ]

as 1 minus the maximum probability of satisfying the formula

  P[ trueU exceeded ]

on the probabilistic timed automaton after the following modifications have been performed.

  -  States in which done is true are forced to make a transition to a sink-location.
  -  Add a transition to a different, ``deadline exceeded'' sink-location, denoted exceeded, as soon as the value of the clock z exceeds D in all states which do not satisfy done).

We first consider the affect that the parameter c has on the performance of the MaxV≥1 algorithm when D=2000 and D=3000.

c:D=2000D=3000
time (s):MaxV≥1 iters:MaxU≥1 iters:time (s):MaxV≥1 iters:MaxU≥1 iters:
1 269.61321,062274.51321,062
10 31.94 15 12633.14 15 126
26 21.60 9 9423.85 9 94
30 27.75 9 9428.87 9 94
40 18.20 7 7822.14 7 78
50 18.67 6 7019.56 6 70
60 201.2 8 91191.8 8 91
70 199.3 8 91217.3 8 91
80 182.4 7 84186.1 7 84
90 179.5 7 84198.6 7 84
100 189.3 7 84186.5 7 84
200 83.67 6 9096.07 6 90
808 659.5 5 115587.8 5 115

We now give the overall model checking time of our implementation in the case the parameter c of the algorithm MaxV≥1 is set equal to 50.

D:MaxV≥1MaxUPRISMminimum probability:
time (s):iters:time (s):iters:states:construction time (s):model checking
time (s):iters:
100015.617025.3523351 2.0720.021 - 0.0
120015.717025.5823351 1.8420.021 - 0.0
140016.047025.9423351 1.8340.02 - 0.0
160015.927025.7223351 1.8360.021 - 0.0
180015.697029.9627441 2.9920.05742 0.583332
200018.677038.8537591 6.4540.07352 0.869791
220015.647054.0346783 11.630.09865 0.966390
240015.597082.1153975 18.690.13475 0.991279
260015.5870118.1611,14329.080.15386 0.997256
280015.6370172.5681,33540.120.20698 0.999298
300019.5670258.7771,52753.690.2281080.999819

Next we give model checking statistics for the approach for computing the maximum probability of satisfying P[ trueU exceeded ] on the modified automaton.

D:MaxUPRISMmaximum probability:
time (s):iters:states:construction time (s):model checking
time (s):iters:
100011.4429 3622.8430.065 - 1
120011.4929 3622.7040.039 - 1
140011.4829 3622.6820.044 - 1
160011.4629 3622.6750.038 - 1
180014.7633 4404.1470.09742 0.416668
200020.0843 5628.2340.12752 0.130209
220037.2452 72213.280.18465 0.033610
240075.3159 88220.040.17775 0.008720
2600103.0671,02227.090.20586 0.002744
2800182.7741,18241.270.24198 7.012e-4
3000261.2831,34253.060.2811081.799e-4

Below are the model checking statistics for the digital clocks approach.

D:constructionmodel checkingminimum probability:
time (s):states:time (s):iters:
1000141.71,876,105 0.2690 0.0
1200243.32,671,305 0.3210 0.0
1400307.83,546,505 0.4410 0.0
1600391.84,501,705 0.4730 0.0
1800445.55,528,692 333.31,8410.583332
2000513.86,570,692 746.22,0300.869791
2200583.57,612,692 1,0522,2520.966390
2400658.28,654,692 1,1592,4680.991279
2600670.29,696,692 1,4722,6570.997256
2800700.210,738,6921,7372,8730.999298
3000764.311,780,6922,0203,0890.999819

We first consider the affect that the parameter c has on the performance of the MaxV≥1 algorithm when D=2000 and D=3000.

c:D=2000D=3000
time (s):MaxV≥1 iters:MaxU≥1 iters:time (s):MaxV≥1 iters:MaxU≥1 iters:
1 660.9 2361,899 666.32361,899
10 78.58 26 219 78.26 26 219
26 93.48 13 136 84.79 13 136
30 86.36 12 128 75.36 12 128
40 73.51 10 108 76.26 10 108
50 81.82 8 92 58.61 8 92
60 270.7 8 91 229.5 8 91
70 270.9 8 91 237.5 8 91
80 272.4 8 88 257.6 8 88
90 271.2 8 88 282.5 8 88
100 256.7 8 88 225.3 8 88
200 1,101 7 94 1,083 7 94
808 103,134 6 217107,167 6 217

We now give the overall model checking time of our implementation in the case the parameter c of the algorithm MaxV≥1 is set equal to 50.

D:MaxV≥1MaxUPRISMminimum probability:
time (s):iters:time (s):iters:states:construction time (s):model checking
time (s):iters:
100058.0692174.5 16 724 13.770.024- 0.0
120063.0392179.3 16 724 13.380.024- 0.0
140072.6192187.9 16 724 13.350.024- 0.0
160063.2692181.2 16 724 13.360.023- 0.0
180059.27921,371 191,20346.470.066360.387618
200081.83925,564 241,76099.300.091420.837514
220060.50926,394 292,170164.70.129510.972994
240058.91929,267 342,578227.40.172590.994852
260077.00921,2258362,935289.90.213650.998839
280065.12921,5088403,343363.10.258730.999791
300058.20921,6878443,751557.50.299800.999960

Next we give model checking statistics for the approach for computing the maximum probability of satisfying P[ trueU exceeded ] on the modified automaton.

D:MaxUPRISMmaximum probability:
time (s):iters:states:construction time (s):model checking
time (s):iters:
1000171.821 737 18.2320.040- 1.0
1200169.021 737 18.3160.041- 1.0
1400163.021 737 18.5720.041- 1.0
1600164.021 737 18.51 0.041- 1.0
1800589.9251,20863.3090.126360.612381
20001,374301,751135.440.176420.162485
22002,104352,145219.560.222510.027004
24003,301402,537296.640.269590.005147
26005,144412,880383.480.311650.001159
28007,875463,272486.720.369732.071e-4
30009,835503,664603.340.445800.380e-4

Below are the model checking statistics for the digital clocks approach.

D:constructionmodel checkingminimum probability:
time (s):states:time (s):iters:
1000238 4,170,287 0.4310 0.0
1200331 5,813,169 0.5190 0.0
1400442 7,535,969 0.4660 0.0
1600532 9,338,769 0.5780 0.0
1800639 11,211,180512.11,8350.387618
2000727 13,072,5801,1802,0200.837514
2200818 14,930,1801,7772,2340.972994
24001,03616,787,7802,1702,4480.994852
26001,37918,645,3802,8182,6330.998839
28001,97320,502,9805,4762,8430.999791
30001,26122,360,5804,9413,0510.999960

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